Formal Verification of SystemC Designs using the BLAST Software Model Checker

SystemC is widely used in hardware/software codesign. Although it is also used for the design of safety-critical applications, existing formal verification techniques for SystemC are still hardly used in industrial practice. The main reasons for this are scalability issues, the lacking support for many practically relevant SystemC language constructs, and that counter-examples are not always easy to use for debugging. In this paper, we present an approach for the formal verification of SystemC designs using the BLAST model checker. The main advantages of our approach are: First, we enable a fully automatic verification of SystemC designs that makes use of counter-example guided abstraction refinement. Second, we support a large subset of SystemC, including pointers, arrays, and structs. Third, we ease debugging by keeping the structure of the design transparent to the designer. We demonstrate the applicability of our approach with experimental results from an Anti-Slip Regulation and Anti-Lock Braking system.